1. Field of the Invention
The present invention generally relates to integrated circuits and, more specifically, to at-speed testing of scan circuits having interacting synchronous clock domains.
2. Description of Related Art
Scan circuits consist of logic and memory elements which are configurable in a shift mode and a capture mode. Scannable memory elements are organized into scan chains. Shift mode is used to load test patterns into scan chains in a circuit and unload circuit responses from the circuit. Capture mode is used to capture circuit responses to the test patterns or scan vectors.
Delay tests are performed by launching a signal transition from a source memory element and capturing the effect of the signal transition at a destination memory element. Two methodologies are used to perform delay tests: launch-on-shift, also known as “single capture”, and launch-on-capture also known as “double capture”. Performing delay tests on Interacting synchronous clock domains present particular problems.
U.S. Pat. No. 5,349,587 issued on Sep. 20, 1994, for “Multiple Clock Rate Test Apparatus for Testing Digital Systems” U.S. Pat. No. 6,145,105 Issued on Nov. 7, 2000 for “Method and Apparatus for Scan Testing Digital Circuits” and U.S. Pat. No. 6,115,827 issued on Sep. 5, 2000 for “Clock Skew Management Method and Apparatus, all incorporated herein by reference, disclose methods of testing circuits having interacting clock domains.
Nadeau-Dostie et al. U.S. Pat. No. 5,349,587 discloses a method for testing paths between memory elements that are clocked by different clocks which are synchronous to each other using the launch-on-shift method. Paths from a lower frequency domain to a higher frequency domain are tested for a propagation time equal to the period of the lower-frequency clock. While this test provides fair coverage of delay defects and simplifies the analysis of the circuit (the circuit to be analyzed is combinational, i.e., sequential depth is 0), it is sometimes desirable to test for a propagation time equal to the period of the higher-frequency clock. The patent does not disclose a method by which this can be achieved. Another limitation of the method is that it does not address the case for which launch-on-capture clocking methodology is used.
Other known methods test for cross-domain path propagation times equal to the period of the highest frequency clock, but the sequential depth of the circuit is such that the coverage of delay defects is relatively low and the circuit analysis time for fault simulation and test generation is prohibitive.